The present invention relates to an address decoder and a semiconductor memory device using the address decoder, and more specifically to an address decoder used for a semiconductor memory device by which a plurality of data can be written simultaneously to a plurality of cells so as to be suitable for use in an image memory.
In general, in the conventional semiconductor memory device having a plurality of memory cells, an inputted address signal is decoded by an address decoder to select a memory cell designated by an address corresponding to the inputted address signal. In the case of a conventional address decoder, when an address signal A.sub.3 A.sub.2 A.sub.1 A.sub.0 is inputted, inverted address value signals A.sub.i (i=0, . . . 3) are generated on the basis of address value signals, A.sub.3, A.sub.2, A.sub.1, representative of the respective bit values of the inputted address signal and cell selection signals Y.sub.j (j=1, . . . 15) corresponding to the address signals A.sub.3 A.sub.2 A.sub.1 A.sub.0 are generated by combination of the address value signals A.sub.1 and the inverted address value signals A.sub.i using AND gates. Here Y.sub.j represents Y.sub.j =X.sub.3 .multidot.X.sub.2 .multidot.X.sub.1 .multidot.X.sub.0, where the respective X.sub.i (i=0, . . . 3) represent A.sub.i or A.sub. i .
In the conventional semiconductor memory device including the address decoder as described above, since the inputted address signals correspond one to one to the output signals of the address decoder, when data are written to the cells, a data can be written in only a cell corresponding to each address. Therefore, it takes much time to clear all the data stored in a plurality of cells or in a part of the plural cells; that is, when the same data are written to the plural cells.
To overcome this problem, a flash write circuit as shown in FIG. 1 is incorporated in the semiconductor memory device in order to write the same data to a plurality of cells simultaneously. In the flash write circuit of the prior art semiconductor memory device, there are provided NOT gates 50 arranged for a pair of bit lines BL and BL, respectively; transistors 52 whose source and drain are connected between the output sides of the NOT gates and the bit lines BL, respectively; a flash write data line g to which the input sides of the NOT gates 50 are connected in common; and a flash write control line h to which the gates of the transistors 52 are connected in common. In this circuit, when a control signal for flash write is transmitted through the control line h, the transistors 52 are turned on, so that data to be written transmitted through the data line g are given to the bit lines BLof pairs of the bit lines via the NOT gates 50 and the transistors 52. In other words, data are written to the bit lines without use of a column address decoder 10. In this operation, if one word line e.g., WL.sub.i) is selected, the same data are written to all the memory cells connected to the word lines WL.sub.i
As described above, in the prior art semiconductor memory device, the flash write function is the simultaneous data writing operation for each row address unit. Therefore, it is possible to clear all the data of the memory or clear the data for each row address unit at high speed. However, there exists a problem in that it is impossible to write data to a part of cells arranged in the column direction at high speed, that is, to implement partial data erasure.